Hierarchical quadrature amplitude modulation (QAM) transmission systems are well known. For example, U.S. Pat. No. 5,966,412, issued Oct. 12, 1999 to Ramaswamy, discloses a modulation system which can remain backward compatible with older quadrature phase shift keyed (QPSK) receivers, while simultaneously further allowing additional data streams, for providing higher data rates or higher precision data, to be receivable by more advanced receivers. FIG. 1 is a block diagram illustrating a hierarchical QAM transmission system as disclosed in this patent. FIG. 1 discloses a data transmitter 100 coupled to a data receiver 300 via a transmission channel 200.
In FIG. 1, a first input terminal DATA 1 is coupled to source (not shown) of a first data signal, and a second input terminal DATA 2 is coupled to a source (not shown) of a second data signal. The first and second data signals may represent separate and independent data, or may represent related data signals, such as signals carrying respective portions of the same data signal (for increasing the throughput of the transmission system) or a elementary data portion and a supplemental data portion of the same data signal (for transmitting enhanced signals while maintaining backward compatibility with existing older receivers, as described in more detail below). The first input terminal DATA 1 is coupled to an input terminal of a first error detection/correction encoder 102. An output terminal of the first encoder 102 is coupled to an input terminal of a level 1 QPSK modulator 104. An output terminal of the level 1 QPSK modulator 104 is coupled to a first input terminal of a signal combiner 106.
The second input terminal DATA 2 is coupled to an input terminal of a second error detection/correction encoder 108. An output terminal of the second encoder 108 is coupled to an input terminal of a level 2 QPSK modulator 110. The level 2 QPSK modulator 110 is coupled to an input terminal of a variable gain amplifier 111, having a gain of G. An output terminal of the variable gain amplifier 111 is coupled to a second input terminal of the signal combiner 106. An output terminal of the signal combiner 106 produces a combined modulated signal and is coupled to the transmission channel 200. In the illustrated embodiment, this channel is a direct satellite television signal transmission system, and the transmission channel includes a ground transmitting station at the transmitter 100 (represented by a transmitting antenna in phantom), a communications satellite (not shown), for receiving the data from the ground station and rebroadcasting that data to a plurality of ground receiving stations, one of which (300) is illustrated in FIG. 1, which receives and processes the rebroadcast data signal, as illustrated by a receiving antenna in phantom.
The output of the transmission channel 200 is coupled to an input terminal of a level 1 QPSK demodulator 302. An output terminal of the level 1 demodulator 302 is coupled to respective input terminals of a first error detection/correction decoder 304 and a delay circuit 306. An output terminal of the first decoder 304 is coupled to an output terminal DATA 1′, and to an input terminal of a reencoder 308. An output terminal of the reencoder 308 is coupled to an subtrahend input terminal of an subtractor 310. An output terminal of the delay circuit 306 is coupled to a minuend input terminal of the subtractor 310. A difference output terminal of the subtractor 310 is coupled to an input terminal of a second error detection/correction decoder 312. An output terminal of the second decoder 312 is coupled to a second data output terminal DATA 2′.
In operation, the first encoder 102 encodes the first data signal DATA 1 to provide error detection/correction capabilities in a known manner. Any of the known error detection/correction codes may be implemented by the encoder/decoder pairs 102/304, 108/312, and those codes may be concatenated, as described in the above mentioned patent. The first encoder 102 produces a stream of encoded bits representing the encoded first data signal DATA 1. The level 1 modulator 104 processes successive sets of two encoded data bits, each set termed a symbol, to generate a QPSK signal which lies in one of four quadrants in a known manner. Similarly, the second encoder 108 encodes the second data signal DATA 2 to provide error detection/correction capabilities in a known manner. The level 2 modulator 110 processes sets of two encoded data bits to also generate a QPSK signal which lies in one of four quadrants. One skilled in the art will understand that additional data signals (DATA 3, etc.) may be respectively error detection/correction encoded by additional encoders and additional QPSK modulators, (level 3, etc.) may be responsive to respective additional sets of two encoded data bits to generate additional QPSK signals. The QPSK signal from the level 1 modulator 104 is given a weight of 1; the QPSK signal from the level 2 modulator 110 is given a weight or gain of 0.5 by the variable gain amplifier 111; the third a weight of 0.25 and so forth. All the weighted QPSK signals are then combined into a single modulated signal by the signal combiner 106 and transmitted through a transmission channel 200.
The level 1 QPSK modulator 104 causes the combined signal to lie within one of four quadrants in response to the set of two encoded data bits from the first encoder 102. Each quadrant, in turn, may be thought of as divided into four sub-quadrants. The level 2 QPSK modulator 110 causes the combined signal to lie within one of the sub-quadrants within the quadrant selected by the level 1 QPSK modulator 104, in response to the set of two input data bits from the second encoder 108. That sub-quadrant may further be though of as divided into four sub-sub-quadrants, and the combined signal caused to lie within one of those sub-sub-quadrants in response to the set of two input data bits from a third encoder (not shown), and so forth.
An older receiver (illustrated in FIG. 1 by a dashed line 300′) includes only a level 1 QPSK demodulator 302, which can detect where in the I–Q plane the received signal lies. From that information, the error detection/correction decoder 304 can determine the corresponding two encoded bits in the received first data stream. The error detection/correction decoder 304 can further correct for any errors introduced by the transmission channel to generate a received data signal DATA 1′ representing the original first data signal DATA 1. Thus, such a receiver can properly receive, decode, and process a first data signal DATA 1 in the presence of additionally modulated data signals DATA 2, (DATA 3), etc. The signals included by the level 2 (and level 3, etc.) QPSK modulators look simply like noise to such a receiver.
A more advanced receiver 300, on the other hand, can detect which quadrant the received modulated signal lies within, and, thus, can receive, decode, and process successive sets of two data bits representing the first data signal DATA 1. The reencoder 308 in the advanced receiver then regenerates an ideal signal lying in the middle of the indicated quadrant, which is subtracted from the received modulated signal. This operation translates the center of the transmitted signal quadrant to the origin. What remains is a QPSK modulated signal, weighted by 0.5, representing the second data signal DATA 2. This signal is then decoded by the second decoder 312 to determine which sub-quadrant the signal lies within, indicating the set of two bits corresponding to that signal. Successive sets of two received data bits representing the second data signal DATA 2 are, thus, received, decoded and processed, and so forth. Such a transmission system operates by modulating a carrier in quadrature with what is seen as a constellation of permissible symbols, and is a form of quadrature amplitude modulation (QAM). Such a system is termed a hierarchical QAM transmission system because it may be used to transmit other levels of data signals, or other levels of detail in a single signal, while maintaining backwards compatibility with older receivers.
FIG. 2a is a diagram illustrating a constellation in the I–Q plane of permissible symbols for a hierarchical 16 QAM transmission system, as illustrated in the above mentioned patent. In FIG. 2a, a first set of two bits determine which quadrant the generated symbol lies within. If the first two bits are “00” then the symbol lies within the upper right hand quadrant, and the level 1 modulator 104 produces I–Q signals such that I=1 and Q=1; if the first two bits are “01” then the symbol lies within the upper left hand quadrant, and the level 1 modulator 104 produces I–Q signals such that I=−1 and Q=1; if the first two bits are “10” then the symbol lies within the lower right hand quadrant and the level 1 modulator 104 produces I–Q signals such that I=1 and Q=−1; and if the first two bits are “11” then the symbol lies within the lower left hand quadrant and the level 1 modulator 104 produces I–Q signals such that I=−1 and Q=−1. This is indicated in FIG. 2a by the appropriate bit pair in the middle of the associated quadrant.
As described above, each quadrant may, itself, be considered to be divided into four sub-quadrants, as illustrated in the upper right hand quadrant in FIG. 2a. The second set of two bits determine which sub-quadrant the symbol lies within. The same mapping is used for determining the sub-quadrant as was described above for determining the quadrant. That is, if the second two bits are “00”, then the symbol lies within the upper right hand sub-quadrant and the level 2 modulator generates an I–Q signal such that I=1 and Q=1; if the second two bits are “01” then the symbol lies within the upper left hand sub-quadrant and the level 2 modulator generates an I–Q signal such that I=−1 and Q=1; if the second two bits are “10” then the symbol lies within the lower right hand sub-quadrant and the level 2 modulator generates an I–Q signal such that I=−1 and Q=−1; and if the second two bits are “11” then the symbol lies within the lower left hand sub-quadrant and the level 2 modulator generates an I–Q signal such that I=−1 and Q=−1. The variable gain amplifier 111 (of FIG. 1) weights the signal from the level 2 modulator 110 by a weight of 0.5, so the points in the sub-quadrants lie at ±0.5 around the center point of the quadrant. Each of these locations is shown as a solid circle in FIG. 2a, with a four bit binary number illustrating the combination of the first and second sets of two bits, with the first two bits being the right hand pair of bits and the second two bits being the left hand pair.
It is known that the bit error rate performance of the respective data streams through the different levels of a hierarchical QAM system such as described above are different. In general, the bit error rate of the level 1 data stream is better than the bit error rate of the level 2 (and higher) data streams. However, the overall performance of the hierarchical QAM transmission system is optimized when the bit error rate of the respective data streams through the different levels are the same. It is desirable, therefore, to optimize not only the overall bit error rate of the transmission system, but also to more closely match the respective bit error rates of the different levels in the transmission system.